2nd

Digital Design year Microelectronics Engineer

ISIM Monastir 2010 - 2011

Chapter VI : More on Gates
I) Introduction:
We will analyze the properties of the logic gate circuits in detail: speed, power consumption, layout design, testability.

II)

Combinational Logic Functions:

It is important to distinguish between combinational logic expressions and logic gate networks. - A combinational logic expression is a mathematical Boolean formula - A logic gate computes a specific Boolean function Why we optimize logic? - We want to find a network that satisfies our area and speed requirements, which may require drastic restructuring of our original logic expression.

̅ ̅ (̅̅̅̅̅̅̅ ) The above example illustrates the relationship between logic expressions and gate network. But we must work with both logic expressions and gate networks to find the best implementation of a function, keeping in mind the relationships:  combinational logic expressions are the specification;  logic gate networks are the implementation;  area, delay, and power are the costs.

III)

Static Complementary Gates:

These gates are static because they do not depend on stored charge for their operations. They are complementary because they are built from complementary networks of p-type and n-type transistors. The important characteristics of a logic gate circuit are its layout area, delay, and power consumption. We will concentrate our analysis on the inverter because it is the simplest gate to analyze.

III.1) Gate Structures:
A static complementary gate is divided into a pull-up network made of p-type transistors and a pull down network made of n-type transistors. The gate’s output can be connected to VDD by the pull-up network or VSS by the pull down network. The two networks are complementary to ensure that the output is always connected to exactly one of the two power supply terminals at any time. VDD

Static Complementary inverter in out

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