Digital Design year Microelectronics Engineer
ISIM Monastir 2010 - 2011
Chapter VI : More on Gates
We will analyze the properties of the logic gate circuits in detail: speed, power consumption, layout design, testability.
Combinational Logic Functions:
It is important to distinguish between combinational logic expressions and logic gate networks. - Acombinational logic expression is a mathematical Boolean formula - A logic gate computes a specific Boolean function Why we optimize logic? - We want to find a network that satisfies our area and speed requirements, which may require drastic restructuring of our original logic expression.
̅ ̅ (̅̅̅̅̅̅̅ ) The above example illustrates the relationship between logic expressions and gate network.But we must work with both logic expressions and gate networks to find the best implementation of a function, keeping in mind the relationships: combinational logic expressions are the specification; logic gate networks are the implementation; area, delay, and power are the costs.
Static Complementary Gates:
These gates are static because they do not depend on stored charge fortheir operations. They are complementary because they are built from complementary networks of p-type and n-type transistors. The important characteristics of a logic gate circuit are its layout area, delay, and power consumption. We will concentrate our analysis on the inverter because it is the simplest gate to analyze.
III.1) Gate Structures:
A static complementary gate is divided into apull-up network made of p-type transistors and a pull down network made of n-type transistors. The gate’s output can be connected to VDD by the pull-up network or VSS by the pull down network. The two networks are complementary to ensure that the output is always connected to exactly one of the two power supply terminals at any time. VDD
Static Complementary inverter in out
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a b c Logic symbol VSS Circuit diagram
III.2) Logic Levels:
A range of voltages near VDD corresponds to logic ‘1’ A range of voltages near VSS corresponds to logic ‘0’
The range in between is X, the unknown value, signals must swing throughthe X region while the chip is operating, no node should ever achieve X as its final value. VOL: voltage produced for logic ‘0’ VOH: voltage produced for logic ‘1’ VIL: the input voltage which will be interpreted as a logic ‘0’ VIH: he input voltage which will be interpreted as a logic ‘1’ If the gates are to work together, we must ensure that VOL < VIL and VOH > VIH. The output voltages producedby a static, complementary gate are VDD and VSS, so we know that the output voltages will be acceptable. (That isn’t true of all gate circuits; the pseudo-nMOS circuit of Section 3.5.1 produces a logic 0 level well above VSS.) We need to compute the values of VIL and VIH
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This figure shows a transfercharacteristic of an inverter simulated using Spice. We define VIL and VIH as the points at which the curve’s tangent has a slope of -1. Between these two points, the inverter has high gain (a small change in the input voltage causes a large change in the output voltage). Outside that range, the inverter has a gain less than 1, so that even a large change at the input causes only a small change at theoutput. The difference between VOL and VIL (or between VOH and VIH) is called the noise margin—the size of the safety zone that prevents production of an illegal X output value. Noise may be introduced by a number of factors: by off-chip connections by capacitive coupling to other electrical nodes from variations in the power supply voltage
III.3) Delay and Transition Time:
VDD There are two...