Diagramme carte mere xenon

Pages: 164 (40959 mots) Publié le: 23 février 2011
SCHEMATIC K7

REV

PB NUMBER X803600-011

VER RETAIL

BOM RELEASE DATE XX/XX/XX

PAGE
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32]

CONTENTS
COVER PAGE CLOCK DIAGRAM RESET/ENABLE DIAGRAM CPU, CLOCKS + EEPROM + STRAPPING CPU, FSB CPU, FSB POWER + PLL POWER CPU, CORE POWER CPU,POWER CPU, DECOUPLING CPU, DECOUPLING CPU, DECOUPLING GPU, FSB GPU, VIDEO + PCIEX + EEPROM GPU, MEMORY CONTROLLER A + B GPU, MEMORY CONTROLLER C + D GPU, PLL POWER + FSB POWER GPU, CORE POWER + MEM POWER GPU, DECOUPLING DUAL ETHERNET PHY MEMORY, A (TOP) MEMORY, A MIRRORED (BOTTOM) MEMORY, B (TOP) MEMORY, B MIRRORED (BOTTOM) MEMORY, C (TOP) MEMORY, C MIRRORED (BOTTOM) MEMORY, D (TOP) MEMORY, DMIRRORED (BOTTOM) ANA, CLOCKS + STRAPPING ANA, VIDEO + FAN + JTAG ANA, POWER + DECOUPLING DEBUG MAPPING, WN DBG VS WN XDK POWER TRACE EMI CAPS

PAGE
[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64]

CONTENTS
SB, PCIEX + SMM GPIO + JTAG SB, SMC SB, FLASH + USB + SPI SB, ETHERNET + AUDIO +SATA SB, STANDBY POWER + DECOUPLE SB, MAIN POWER + DECOUPLE SB OUT, ETHERNET SB OUT, AUDIO SB OUT, FLASH SB OUT, FAN + INFRARED + BUTTONS CONN, AVIP CONN, RJ45 + USB COMBO CONN, GAME PORTS + MEMORY PORTS BACKUP CLOCK + V_5P0 DUAL CONN, ODD AND HDD CONN, ARGON + POWER VREGS, INPUT + OUTPUT FILTERS VREGS, CPU CONTROLLER VREGS, GPU OUTPUT PHASE 1,2,3 VREGS, GPU CONTROLLER VREGS, GPU OUTPUT PHASE 1,2VREGS, SWITCHED 1.8, 5.0V VREGS, LINEAR REGULATORS XDK, DEBUG CONN DEBUG BOARD, CPU + GPU BREAKOUT DEBUG BOARD, CPU CONN DEBUG BOARD, CPU CONN + TERM DEBUG BOARD, CPU TERM DEBUG BOARD, TITAN + YETI CONN DEBUG BOARD, GPU CONN + TERM XDK, LEDS LABELS AND MOUNTING

XENON
RETAIL
REV K7 FAB K

RULES: 1.) 2.) 3.) 4.) 5.) 6.) 7.) 8.) 9.) 10.) 12.) 13.) 14.) 15.)

(APPLIED

WHEN POSSIBLE)

MSBTO LSB IS TOP TO BOTTOM WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS LANED SIGNALS ARE GROUPED ON SYMBOLS TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS UNNAMED NETSARE NAMED WITH /2 TEXT SIZE SUFFIX _N FOR ACTIVE LOW OR N JUNCTION SUFFIX _P FOR P JUNCTION SUFFIX _EN FOR ENABLE 'CLK' FOR CLOCKS, 'RST' FOR RESETS PWRGD FOR POWER GOOD
DRAWING

XENON
PLEASE REFER TO THE XENON DESIGN SPEC
BOM RELEASE DATE
XX/XX/XX

PB NUMBER

X803600-011

SIGNATURE DRN BY CHK BY ENGR APVD APVD

DATE

MICROSOFT
TITLE

XBOX
XENON
PAGE 1/73 REV K7

SCH,MICROSOFT CONFIDENTIAL

PBA,

[PAGE_TITLE=COVER

PAGE]

Wed Aug

XENON_FABK
24

09:41:55

2005

APVD

PROJECT NAME XENON_RETAIL

RJ45/USB CONN

AVIP CONN

FAN CONN

POWER CONN

ENET PHY

ENET_CLK(25MHZ)

CLOCK DIAGRAM
AUDIO DAC ANA_XTAL_IN(27MHZ) GPU VR ANA BCKUP

I2S_MCLK(12.288MHZ) I2S_BCLK(3.072MHZ)

DEBUG CONN

ANA
GPU VR CNTL

SB
DVD SATA CONNSTBY_CLK(48MHZ) SATA_CLK_REF(25MHZ) SATA_CLK_DP/DN(100MHZ) PCIEX_CLK_DP/DN(100MHZ) AUD_CLK(24.576MHZ) CPU_CLK_DP/DN(100MHZ) GPU_CLK_DP/DN PIX_CLK_OUT_DP/DN(100MHZ) (100MHZ)

RISCWATCH CONN

DVD PWR CONN ANA BCKUP MEM CLAM C+D

MC_CLK1_DP/DN(800MHZ) MC_CLK0_DP/DN(800MHZ) MD_CLK1_DP/DN(800MHZ) MD_CLK0_DP/DN(800MHZ)

GPU
MA_CLK1_DP/DN(800MHZ) MA_CLK0_DP/DN(800MHZ) MB_CLK1_DP/DN(800MHZ)MB_CLK0_DP/DN(800MHZ)

CPU

CPU VR

1P8

VR FLSH

HDD CONN

3P3

VR VMEM VR MEM CLAM A+B EFUSE VR

TITAN CONN

JTAG

MPORT VR

5P0

VR

CPU VR CNTL

GAME CONN IR EJECT SW MEM CONN MEM CONN BIND SW ARGON CONN

DRAWING XENON_FABK Wed Jul 27 21:53:30

2005

MICROSOFT CONFIDENTIAL

PROJECT NAME XENON_RETAIL

PAGE 2/73

REV K7

RJ45/USB CONN

AVIP CONN

FAN CONN...
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